1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor devices and, more specifically, to alignment during semiconductor fabrication. More particularly still, the present invention relates to the use of a resist latent image as a diffraction grating for the aligning and patterning of field oxide, and relates to the use of field oxide step heights for alignment during the fabrication of circuit devices.
2. State of the Art
One area involving constant improvement in semiconductor device fabrication is in the area of photolithography. Presently utilized semiconductor device processing methods require numerous photolithography steps. Thus, photolithography is one of the most critical operations in semiconductor device processing.
Photolithography is essentially a patterning process which determines the horizontal dimensions on the various components of the semiconductor devices (i.e., circuit components) by creating a mask on a particular material layer (disposed on or over a semiconductor wafer) of the semiconductor device and etching portions of the material layer through the mask to form a pattern on that material layer. The dimensions of the pattern are referred to as the image sizes of the circuit components.
Since the material layers are sequentially built up and patterned to form the semiconductor device, the photolithographic patterning process requires proper placement or alignment of each pattern on each particular material layer of the semiconductor device. The patterns formed on the various material layers must be correctly aligned and the individual parts of the circuit components must be correctly positioned relative to each other for the semiconductor device to function properly.
Naturally, the image size and pattern alignment in photolithography are interrelated. As the image size decreases, the alignment of the patterns must be more precise. Of course, image size will continue to decrease, because increased miniaturization of components and greater packaging density of integrated circuits are ongoing goals of the computer industry. Thus, as circuitry components become smaller and smaller, alignment must become more precise during masking steps to minimize the misalignment between patterned, material layers utilized in forming the circuitry components.
Most alignment schemes require the use of alignment targets that are defined on the semiconductor wafers and/or a previous material layer. One such scheme involves two alignment targets that are defined on the semiconductor wafer with all subsequent layers being aligned, either directly or indirectly, with these alignment targets. These alignment targets are used to diffract a laser alignment beam generated by a photolithographic machine, commonly known as a wafer stepper, during the masking process. The diffraction pattern is received by the wafer stepper and the relative positions of the semiconductor wafer and a photolithographic mask are adjusted accordingly so that the patterns from the photolithographic mask are transferred to the semiconductor wafer in the precise location as desired.
Subsequent layers, such as conductive material (i.e., metallization) or dielectric layers, are formed during the circuit fabrication in a similar fashion. In order to minimize misalignment between layers, it is important that the topography of these alignment targets be replicated from one layer to the next, since the locations of the resulting patterns on each material layer are formed based on the precise registration between the photolithographic mask and the alignment targets on the previous material layer.
For metallization layers, it is generally important to provide a surface that is as flat or planar as possible. Thus, the surface of the layer is smooth in preparation for subsequent metallization layers by the process known as planarization. Conventional planarization techniques include plasma etching or the reactive ion etching (RIE) of oxides with a resist planarizing medium. New techniques include abrasive planarizing in the form of chemical-mechanical polishing/planarizing (xe2x80x9cCMPxe2x80x9d) which involves holding the semiconductor wafer against a rotating polishing pad wetted with a silica-based alkaline slurry and at the same time applying pressure. The CMP techniques provide a global planarization that covers the whole surface of the semiconductor wafer. Since the planarization range is large, the alignment targets on a newly formed layer on the semiconductor wafer will lose their steps after it is planarized. The CMP technique fails to replicate the alignment targets on the previous layer that is beneath the newly formed layer. This is acceptable only if the planarized, newly formed layer is transparent, such as in the case of silicon dioxide, since the laser or alignment beam from a wafer stepper and the corresponding diffraction pattern can pass through such a transparent layer. However, when the planarized, newly formed layer is highly reflective or opaque, such as in the case of a metal layer, the alignment targets are not visible to the wafer stepper. In such a case, new alignment targets have to be formed on the newly formed layers using a process commonly known as the window mask process.
Window mask processing involves exposing the alignment targets only while the remaining semiconductor wafer surface is covered by photoresist. The semiconductor wafer is then subjected to an oxide step of sufficient duration so that the amount of silicon dioxide removed during this etch, plus the amount of silicon dioxide to be removed during the subsequent etch, exposes the step pattern of the underlying target. This allows the metal to replicate the topography of the step patterns of the underlying alignment targets when the metal is deposited. This technique forms a new set of alignment targets. Accordingly, the wafer stepper is able to perform alignment between a photolithographic mask, the semiconductor wafer and the next photolithographic process.
By way of example only, the following discussion will focus on the formation of a twin-well CMOS (Complementary Metal Oxide Semiconductor) structure using standard alignment marks. FIG. 21 illustrates a semiconductor wafer 202 in which alignment marks 204 have been formed in an active surface 206 at a location proximate an edge 208 of the semiconductor wafer 202. These alignment marks 204 are used to align the patterning of masks and implantation tools, as known in the art, to form p-wells 212 and n-wells 214 abutting the active surface 206 of the semiconductor wafer 202. The individual electrical devices are generally isolated using a LOCOS (LOCal Oxidation of Silicon) technique.
The LOCOS technique begins with forming a layer of silicon dioxide 218, usually between about 20 and 50 nm thick, on the active surface 206 of the semiconductor substrate 202, as shown in FIG. 22. After the formation of the silicon dioxide layer 218, a layer of silicon nitride 222, usually between about 100 and 200 nm thick, is deposited, generally by CVD, over the silicon dioxide layer 218 to function as an oxidation mask. The alignment marks 204 must be re-exposed in order that they are detected for alignment purposes. This can be achieved by removing a portion of the silicon nitride layer 222 and silicon dioxide layer 218 over the alignment marks 204.
Active areas 232 are then defined with photolithographic and etch steps illustrated in FIGS. 23 through 27. As shown in FIG. 23, a photoresist layer 224 is patterned on the silicon nitride layer 222 to protect all of the areas where active areas will be formed, wherein the photoresist layer 224 pattern is aligned using the alignment marks 204. The silicon nitride layer 222 and the silicon dioxide layer 218 are then etched, and any remaining photoresist layer 224 is removed, as shown in FIG. 24. A barrier layer 225 is preferably formed over the alignment marks 204 to prevent silicon dioxide formation on the alignment marks 204 in subsequent formation of isolation structures, as also shown in FIG. 24. As shown in FIG. 25, an isolation structure or field oxide 226 is formed, usually thermally grown by wet oxidation at elevated temperatures.
The silicon nitride layer 222 and barrier layer 225 are then removed to expose the silicon dioxide layer 218 and the alignment marks 204, respectively, as shown in FIG. 26. The field oxide 226 and silicon dioxide layer 218 are etched to remove the silicon dioxide layer 218 and expose active areas 232 on the p-wells 212 and n-wells 214, as shown in FIG. 27.
The active areas 232 are then used to form individual electrical devices, such as PMOS, NMOS, and CMOS transistors. For purposes of illustration, FIG. 27 also shows semiconductor-layer source regions and drain regions for a CMOS transistor. The implantation of the source regions and the drain regions is usually achieved with a double masking process wherein a first mask is applied over the active area over the n-wells 214 and an n-type impurity is introduced to the exposed active areas over the p-wells 212 to form n-type areas 236. The first mask is removed and a second mask is applied to the active areas over the p-wells 212 and a p-type impurity is introduced to the exposed active areas over the n-wells 214 to form p-type areas 238. The second mask is then removed to form the structure shown in FIG. 27. The n-type areas 236 and the p-type areas 238 are subsequently used as source/drain areas in further CMOS fabrication. Throughout this process, care must be taken to be sure that the alignment marks remain exposed in order to align the first and second mask.
The CMOS is further fabricated with the formation of gates 258 (FIG. 31) between each source and drain region. FIGS. 27 through 31 illustrate, in cross section, a conventional method of forming the gates 258. FIG. 28 illustrates a gate dielectric layer 244 such as silicon dioxide grown (by oxidation) or deposited (by any known industry standard technique, such as chemical vapor deposition or the like) over the active areas and the field oxide 226. A conductive material layer 246 is deposited over the gate dielectric layer 244, and a cap layer 248, such as silicon dioxide, is deposited on the conductive material layer 246. At this point, a photoresist layer must be positioned or patterned properly on the cap layer 248 in order to form the gates in their proper location. However, the alignment marks 204 must again be exposed (as shown in FIG. 29), such as by masking and etching, in order to align the subsequent photoresist layer pattern. Once the alignment marks 204 are exposed, the photoresist layer 252 can be patterned, as shown in FIG. 29. The cap layer 248, the conductive material layer 246, and the gate dielectric layer 244 are then etched to form gate stacks 254 as shown in FIG. 30. A conformal layer of dielectric material (not shown), such as silicon nitride, is formed over the gate stacks 254 and anisotropically etched to form the spacers 256 on the side of the gate stacks 254, thereby forming gates 258, as shown in FIG. 31.
Because of the difficulties in preserving the alignment targets between layers, it is often desirable to use other alignment techniques. These alignment techniques might be found in other fields that use light diffraction. One such diffraction-based technique has been pursued in the field of exposure dose control to minimize the difficulty in controlling the photoresist application and exposure steps. These control problems are further outlined in Milner et al., Stepper Focus Characterization Using Diffraction From Latent Images, J. Vac. Sci. Technol. B, Vol. 11, No. 4, July/August 1993, pp. 1258-1266, which describes the use of resist latent images as a diffraction grating in performing stepper focus. The diffraction grating pattern comes from a latent image formed in exposed, undeveloped photoresist material. Other experimental uses of resist latent images in image alignment have only recently been undertaken and include performing focus measurement, alignment, and projection system setup.
In view of the foregoing, it would be advantageous to develop a method of fabricating semiconductor components that eliminates the necessity for independent or separate alignment marks, thereby eliminating problems associated therewith, by utilizing the resist latent images and structures inherent in the formation of the integrated circuits to achieve alignment.
The present invention relates to the use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and to the use of field oxide step heights for alignment during the fabrication of circuit devices.
One embodiment of the present invention involves the use of a resist latent image alignment mark. For example, this embodiment may be used in the fabrication of MOS (Metal Oxide Semiconductor) structures. In such a fabrication, a layer of silicon nitride is deposited over the silicon dioxide layer found on an active surface of a semiconductor substrate. A layer of photoresist material is then applied over the silicon nitride layer. An alignment pattern is formed in an appropriate position in the photoresist material layer by forming a latent image in the photoresist material layer. The latent image is formed by bleaching the undeveloped photoresist material layer by exposure to a specific light pattern.
The photoresist material layer is then selectively exposed to a radiation source through a mask having a desired aperture pattern defined therein by aligning the mask over the photoresist material layer with the alignment pattern. This results in the photoresist material being patterned on the silicon nitride layer to protect all of the areas where active areas will be formed. The silicon nitride and silicon dioxide layers are etched to expose portions of the semiconductor substrate. An isolation structure may then be thermally grown by wet oxidation in the exposed portions of the semiconductor substrate.
Advantageously, the need for alignment targets formed on a semiconductor wafer and the problems associated with use of such targets are eliminated through the use of a latent image in the photoresist material layer.
Another embodiment of the present invention includes the use of isolation structures or field oxides as alignment targets. The proper control of field oxide growth is critical to this embodiment in that the step heights of the field oxide can be formed to act as a diffraction grating for stepper alignment. For example, with a stepper alignment laser wavelength of about 633 xc3x85, the optimal step height is about 1266 xc3x85. Thus, by way of example, the field oxide can be grown to an initial total height of about 3700 xc3x85 wherein approximately 45% of the total height extends into the semiconductor substrate to yield a first step height about 1665 xc3x85. The silicon nitride layer is then removed to expose the silicon dioxide layer. The field oxide and silicon dioxide layer are etched to remove the silicon dioxide layer and expose active areas on the semiconductor substrate. This results in a second step height (from the top of the field oxide to the semiconductor substrate) of approximately 1155 xc3x85.
Since the field oxide is essentially transparent to a stepper alignment laser, the first step height is used to align a stepper to implant the p-wells and n-wells, as well as align a stepper to implant n-type areas and p-type areas that are subsequently used as source/drain regions.
The CMOS is further fabricated with the formation of gates between each source and drain region. A gate dielectric layer is disposed over the active areas and the field oxide. A conductive material layer is deposited over the gate dielectric layer, and a silicon dioxide cap layer is deposited on the conductive material layer. At this point, a photoresist layer must be patterned properly on the silicon dioxide cap layer in order to form the gates in their proper location. However, the conductive material layer will prevent the alignment of the photoresist pattern to the first step height.
As discussed above, the second step height was purposefully formed to be approximately 1155 xc3x85, which is within an acceptable range of the optimal 1266 xc3x85 step height for reliable alignment performance. Since the gate dielectric layer, the conductive material layer, and the silicon dioxide cap layer are conformal, the second step height is translated to each of these layers. Thus, the third step height of the conductive material layer becomes the step height for alignment of the resist pattern for etching to form gate stacks. A conformal layer of dielectric material, such as silicon nitride, is applied over the anisotropically etched gate stacks to form the spacers on the side of the gate stacks, thereby forming gates.
In yet another embodiment of the present invention, a layer of opaque material is deposited over the active areas and the field oxide. The gate dielectric layer is deposited over the opaque material; a conductive material layer is deposited over the gate dielectric layer; and a silicon dioxide cap layer is deposited on the conductive material layer. A photoresist layer is then patterned on the silicon dioxide cap layer in order to form the gates in their proper location. The conductive material layer, however, will prevent the alignment of the photoresist pattern to the first step height.
Again, as discussed above, the second step height was purposefully formed to be approximately 1155 xc3x85, which is within an acceptable range of the optimal 1266 xc3x85 step height for reliable alignment performance. Since the opaque material layer, the gate dielectric layer, the conductive material layer, and the silicon dioxide cap layer are conformal, the second step height is translated to each of these layers. Thus, the third step height of the conductive material layer becomes the step height for alignment of the resist pattern for selectively etching to form gate stacks atop the opaque material layer. A conformal layer of dielectric material, such as silicon nitride, is applied over the gate stacks and the opaque material layer is anisotropically etched to form the spacers on the side of the gate stacks, thereby forming gates.
A barrier dielectric material, which is substantially transparent to the laser light being used for alignment, is deposited over the opaque material layer and the gates, and is preferably planarized. Since the barrier dielectric material is substantially transparent to the laser light being used for alignment, a step height of the opaque material layer (which is the same as the second step height as translated thereto) may be used to pattern a second photoresist material. The barrier dielectric material is etched to form vias. The vias are filled with a conductive material to form conductive contacts for subsequent formation of capacitors and bitlines.
It is, of course, understood that the opaque material layer could be utilized in lieu of the first step height of the field oxide for the alignment of the stepper to implant the p-wells and n-wells, as well as alignment of a stepper to implant n-type areas and p-type areas to be used as source/drain regions, wherein the implantations occur through the opaque material layer.